The present invention relates to the fabrication of semiconductor integrated circuits, and more specifically to a method of altering the stress of a thin film and complementary metal oxide semiconductor (CMOS) transistor structures which are formed with such stress altered film.
Thin layers of film are used in the semiconductor industry to alter or enhance the characteristics of adjacent and underlying or base layers. The film may be comprised of a variety of materials chosen selectively to provide certain advantages. Among of the advantages provided by a particular film are a desirable thickness, longevity and dielectric strength, as well as the ability to withstand temperatures. A layer of film can also enhance conformity of deposition of other layers, or provide gap filling characteristics or enhance planarity. Some such films, although desirable in some respects, have an undesirable stress present in them.
However, in certain circumstances, stress may be desirable in the film if applied selectively. Such is the case in complementary metal oxide semiconductor (CMOS) technology. CMOS transistors, for example, are used in some types of static random access memory (SRAM) and in logic circuitry. The term “CMOS transistors” is understood to include the two complementary types of field effect transistors (FET) known as n-type and p-type FETs. To create the two complementary FETs, the conductivity of the semiconductor material is altered and controlled by application of electrical field. CMOS circuitry, utilizes both n-type FETs and p-type FETs devices with different types of carriers.
Traditionally, performance gains for CMOS circuits have been produced by shrinking the gate dimension and thinning the gate oxide. However, with the advent of new technology this approach is becoming less desirable due to its physical limitations. An alternative approach is to introduce structures that enhance electron mobility in n-type transistors and enhance hole mobility in p-type transistors.
Both theoretical and empirical studies have demonstrated that charge carrier mobility in a transistor can be greatly increased when a stress of sufficient magnitude is applied to the conduction channel of a transistor to create a strain therein.
Strain can be either tensile or compressive. In p-type field effect transistors, the application of a compressive longitudinal stress, i.e. in the direction of the current flow in the conduction channel, creates a strain in the conduction channel which is known to increase the drive current of a PFET. However, if that same stress is applied to the conduction channel of an NFET, its drive current decreases.
Performance of an NFET and a PFET can be greatly improved by applying a tensile longitudinal stress to the conduction channel of an NFET and applying a compressive longitudinal stress to the conduction channel of a PFET. Prior art methods have been unsuccessful in providing an effective process to modify stress in compressive and tensile channel regions at the same time. Accordingly, it would be desirable to provide a single process for creating a desired compressive strain in the channel region of a PFET without creating the same strain in the channel region of the NFET, and to create a desired tensile stress in the channel region of an NFET without creating the same strain in the channel region of a PFET.
Other than its application to CMOS or even the semiconductor industry, the development of a process that can selectively relax a film by reducing the stress present in certain areas of a film can have widespread benefits. The performance of microstructures and nanostructures such as microelectronics components and micro-electromechanical machines can be greatly enhanced by the application of such a process to a stressed film. Therefore, it is desirable to develop a process to relax the stress present in a film in selected areas.